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921E High-Rate Multichannel Buffer

Specifications

PERFORMANCE

ADC  Successive-approximation type with sliding-scale linearization.

MAX RESOLUTION  16,384 channels, software selectable as 16,384, 8192, 4096, 2048, 1024, and 512.

DEAD TIME PER EVENT  1.5 µs, including memory transfer; measured at 5 µs shaping with ORTEC Model 973 High-Rate Spectroscopy Amplifier at 100,000 counts/sec input count rate.

INTEGRAL NONLINEARITY  ±0.025% over the top 99% of the dynamic range.

DIFFERENTIAL NONLINEARITY  ±1% (typical).

GAIN INSTABILITY  ±50 ppm/°C.

DEAD TIME CORRECTION  Extended Live Time correction according to Gedcke-Hale method.3

DATA MEMORY  16k channels of NON-volatile memory; 231–1 (over 2 billion) counts per channel.

PRESETS

Real Time/Live Time  Multiples of 20 ms.

Region of Interest  Peak count/integral count.

Data Overflow  Terminates acquisition when any channel exceeds 2 billion.

Peak Uncertainty

Nuclide MDA

DIGITAL SPECTRUM STABILIZER  Peak centroid stabilization: either zero, gain, or both. Window width, for both zero and gain: ±1 to ±256 channels.

Correction Resolution  At 16k ADC resolution: 0.04 channels (for gain); <0.08 channels (for zero).

ADC Word Size  14 bits (16k channels) maximum.

Setup/Enable/Disable  From computer.

FRONT-PANEL INDICATORS

CPU BUSY  Red, busy-rate LED; intensity indicates the relative activity of the microprocessor.

STAB BUSY  Red LED indicates when stabilizer is active.

ADC BUSY  Red, busy-rate LED flashes once for each pulse digitized by ADC.

CONTROLS

ADC ZERO  Screwdriver potentiometer adjusts ADC zero offset ±250 mV.

ADC LLD  Screwdriver potentiometer adjusts lower level discriminator from 0 to 10% of full scale.

INPUTS

INPUT  Accepts positive unipolar, positive gated integrator, or positive leading bipolar analog pulses in the dynamic range from 0 to +10 V; +12 V maximum; semi-Gaussian-shaped or gated-integrator-shaped time constants from 0.25 to 30.0 µs, or delay-line-shaped with width >0.25 µs. Zin ~ 1000 Ω, dc-coupled. No internal delay. BNC connector on front and rear panel.

ADC GATE  Optional, slow-positive NIM input. Computer-selectable Coincidence or Anticoincidence. Signal must occur prior to and extend 0.5 µs beyond peak detect; front-panel BNC connector.

PUR  Pile-up rejection input; accepts slow-positive NIM signal; signal must occur prior to peak detect. Zin > 1 kΩ. BNC connector on rear panel.

BUSY  Busy input used by live-time correction circuits. Accepts slow positive NIM  signal, Zin > 1 kΩ. BNC connector on rear panel.

SAMPLE READY  TTL input signal to BNC connector on rear panel.

OUTPUTS

CHANGE SAMPLE  TTL output signal to BNC connector on rear panel; software addressable.

INTERFACES4

ETHERNET  Rear-panel BNC connector, accepts IEEE 802.3 10BASE2 (thin-wire coax).

ELECTRICAL AND MECHANICAL

POWER REQUIRED  +24 V, 160 mA; –24 V, 240 mA; +12 V, 900 mA; –12 V, 260 mA; +6 V, 1.0 A.

WEIGHT
Net  2.25 kg (5 lb).
Shipping  3.1 kg (7 lb).

DIMENSIONS  NIM-standard double-wide 6.90 x 22.13 cm (2.70 x 8.714 in.) front panel per DOE/ER-0457T.

ORDERING INFORMATION

Model   Description
921E   921 EtherNIM™ High-Rate Multichannel Buffer

3Ron Jenkins, R.W. Gould, and Dale Gedcke, Quantitative X-Ray Spectrometry (New York: Marcel Dekker, Inc.) 1981, pp 266–267.

4The following connectors are also available:
Dual-Port Memory — ORTEC dual-port memory, 37-pin D connector.
RS-232-C — Serial standard RS-232-C 25-pin; male wired as DTE to run at 38.4 kbaud maximum, with modem control. Software selectable baud rate. (For diagnostics)