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572A AMPLIFIER
The ORTEC Model 572A Amplifier is ideally suited for use with germanium detectors, silicon charged-particle detectors, proportional counters, scintillation counters, and pulsed ion chambers. It includes an automatic gated baseline restorer and built-in pile-up rejector to provide exceptionally stable performance over a very wide dynamic range. System resolution is nearly independent of input counting rate (Fig. 1).
Fig. 1 Typical Resolution and Baseline Stability vs Counting Rate for the Model 572A in a Gamma Spectroscopy System The gated baseline restorer (BLR) includes a discriminator that operates the sensing circuits that normally establish the baseline reference of the MCA. Performance of the spectrometer depends on the precision of the setting of the BLR threshold. The Model 572A offers the convenience of an automatic threshold control, which typically gives as good or better results than those the most experienced operator could achieve manually. The gate logic generates a Busy signal that can be used for dead-time correction. The active filter networks permit the Model 572A to generate very symmetrical unipolar outputs with optimum signal-to-noise ratios over a wide range of time constants. The instrument also provides a bipolar output for timing and gating applications. Any dc drift in an amplifier output causes spectrum broadening. The excellent dc stability of the Model 572A eliminates spectrum broadening caused by dc drift and ensures that the high resolution capability of germanium detectors is realized. Pile-Up Rejector: The pile-up
rejection circuit incorporated into the Model 572A generates an inspection period
immediately following every signal equal to the duration of the Busy output. If a second
event were to occur within this inspection interval, an inhibit signal, INH Output, would
be generated to gate-off the MCA and thus discard the distorted amplifier output. Figure 2
shows the background reduction that takes place ina gamma ray spectrum as pile-up
rejectionis used. Figure 3 illustrates the timing relationship between the amplifier
input, output, and pile-up rejector logic signals.
Fig. 2 Background Reduction Obtained from Pile-Up Rejection.
Fig. 3 Amplifier and Pile-Up Rejector Signals. ORDERING INFORMATION
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