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ADC Types
Three types of ADCs are available: the flash ADC, the Wilkinson ADC,
and the successive-approximation ADC. Only the latter two are used
for high-resolution pulse-height spectroscopy.
The Wilkinson ADC
The operation of the Wilkinson ADC is illustrated in
Figs. 1 and 2. The lower-level
discriminator (Figs. 1a and 1b) is used to recognize the arrival of
the amplifier output pulse. Usually, the lower-level discriminator
threshold is set just above the noise level to prevent the ADC from
spending time analyzing noise. When the input pulse rises above the
lower-level discriminator threshold, the input linear gate is open
and the rundown capacitor is connected to the input (Fig. 2a). Thus,
the capacitor is forced to charge up so that its voltage follows the
amplitude of the rising input pulse (Fig. 1c). When the input signal
has reached its maximum amplitude and begins to fall (Fig. 1c), the
linear gate is closed and the capacitor is disconnected from the
input (Fig. 2b). At this point, the voltage on the capacitor is
equal to the maximum amplitude of the input pulse. Following peak
amplitude detection, a constant current source is connected to the
capacitor to cause a linear discharge (rundown) of the capacitor
voltage (Figs. 1c and 2b). At the same time, the address clock is
connected to the address counter (Figs. 1d and 2b) and the clock
pulses are counted for the duration of the capacitor discharge. When
the voltage on the capacitor reaches zero, the counting of the clock
pulses ceases. Since the time for linear discharge of the capacitor
is proportional to the original pulse amplitude, the number Nc
recorded in the address counter is also proportional to the pulse
amplitude. During the memory cycle (Figs. 1e and 2c), the address Nc
is located in the histogramming memory, and one count is added to
the contents of that location. The value Nc is usually
referred to as "the channel number." ADCs are commonly available
with as few as 256 channels for low-resolution applications, and as
many as 16,384 channels for high-resolution requirements.
For the Wilkinson ADC, the measurement time of the MCA contributes a
non-extending dead time as expressed in
Equation (1).TM = (NC
/ fC) + TMC
(1)
The MCA dead time depends on the clock frequency fc,
the channel number Nc, and the memory cycle time TMC.
Clock frequencies in the range from 50 to 400 MHz are typical, and
memory cycle times from 0.5 to 2 µs are common. As a result, maximum
conversion times for an 8192-channel Wilkinson ADC range from 20 to
165 µs. The advantage of Wilkinson ADCs is low differential
nonlinearity (typically <1%). The disadvantage is the long
conversion time, which is dependent on pulse amplitude.
The Flash ADC
Figure 3 depicts the principle of the flash
ADC. The ADC is constructed by stacking a series of comparators so
that each comparator's threshold is a constant increment in voltage
∆V above the previous threshold. The flash ADC is essentially a
stack of single-channel pulse-height analyzers with equal window
widths and shared thresholds. When the analog input signal is at its
maximum amplitude, the outputs of the comparators are strobed into
the digital output encoder. The illustration in Fig. 3 is a two-bit
(or four-channel) flash ADC. If, for example, the amplitude of the
analog pulse falls between the levels of comparators 2 and 3, the
binary output code generated is 10 (equivalent to the decimal number
2). The advantage of flash ADCs is speed. Conversion times are in
the nanosecond range. The disadvantage is large differential
nonlinearity (non-uniformity of channel widths), which generally
limits the flash ADC to a resolution of less than eight bits.
Because of the large differential nonlinearity and the limited
number of bits, the flash ADC is not applicable for high-resolution
pulse-height spectroscopy.
The Successive-Approximation ADC
The successive-approximation ADC is illustrated in
Fig. 4. During the rise of the analog input
pulse, the switch S1 is closed and the voltage on capacitor C1
tracks the rise of the input signal. When the input signal reaches
maximum amplitude, S1 is opened, leaving C1 holding the maximum
voltage of the input signal. After detection of the peak amplitude
of the input pulse, the successive-approximation ADC begins its
measurement process. First, the most significant bit of the
digital-to-analog converter (DAC) is set. If the comparator
determines that the DAC output voltage is greater than the signal
amplitude Vs, the most significant bit is reset. If the
DAC output voltage is less than Vs, the most significant
bit is left in the set condition. Subsequently, the same test is
made by adding the next most significant bit. This process is
repeated until all bits have been tested. The bit pattern set in the
register driving the DAC at the end of the test is a digital
representation of the analog input pulse amplitude. This binary
number Nc is the address of the memory location to which
one count is added to build the histogram representing the
pulse-height spectrum. If the ADC has n bits (2n
channels), n test cycles are required to complete the
analysis, and this is the same for all pulse amplitudes.
The number of test cycles can be reduced by replacing the single
comparator with a flash ADC. For example, in a 16-bit
successive-approximation ADC a 6-bit flash ADC is used to determine
5 bits in the first cycle, 5 bits in the second cycle, and the
remaining 6 bits in the third cycle. This improves the overall
conversion time by reducing the number of cycles from 16 to 3.
Although successive-approximation ADCs are available with the number
of bits required for high-resolution spectroscopy, their
differential nonlinearity is not adequate. The differential
nonlinearity is typically 1/2 of the least significant bit (i.e.,
50%). This problem is overcome by adding the sliding scale
linearization shown in Fig. 5. After each
pulse is analyzed, the 8-bit counter is incremented. This results in
an analog voltage being added to the analog input signal before
analysis by the successive-approximation ADC. If the number in the
8-bit counter is m, this results in the
successive-approximation ADC reporting the analysis m
channels higher than normal. By digitally subtracting m at
the output of the successive-approximation ADC, the digital
representation is brought back to its normal value. As the 8-bit
counter increments through its range after each input pulse, it
averages the analysis of each pulse height over 256 adjacent
channels in the successive-approximation ADC. This reduces the
differential nonlinearity to <1%.
The advantages of the successive-approximation ADC with sliding
scale linearization are low differential nonlinearity, and a short
conversion time that is independent of the pulse amplitude.
Conversion times in the range from 2 to 20 µs are available, with
ADC resolutions ranging from 1,000 to 16,000 channels.
Figure 1.
Signals in the Wilkinson ADC during the Pulse Measurement
Process.
Figure 2.
Operation of the Wilkinson ADC during the Three Stages of Pulse
Amplitude Measurement.
(a) Charging of the rundown capacitor, (b) capacitor rundown, and
(c) the memory cycle.
Figure 3.
The Principle of a Flash ADC.
Figure 4.
The Basic Circuits used with a Successive-Approximation ADC.
Figure 5.
The Successive-Approximation ADC with Sliding Scale
Linearization. |
