AD114 CAMAC 16k ADC

• 16,128-channel ADC with CAMAC and fast FERAbus™ readout for: single- or multi-parameter experiments, high counting rates, and wide energy ranges
• 5-µs conversion time
• FERAbus readout can skip ADCs with no information in 3 ns, and read each active ADC in 200 ns
• Gedcke-Hale Live-Time Clock includes dead-time correction for amplifier pulse pile-up losses
• CAMAC control of: live-time clock, FERAbus/CAMAC readout, zero and overflow suppression, master gate, local gate, singles/coincidence modes, upper- and lower-level discriminators, and input dc-offset
• Differential input suppresses ground-loop noise

The ORTEC Model AD114 CAMAC 16k ADC is a 14-bit analog-to-digital convert (ADC) with CAMAC and fast FERAbus readout. It is a very productive solution for high-multiplicity multi-parameter experiments, because it has a conversion time of 5 µs, and a 100-ns-per-word FERAbus readout that skips ADCs with zero information in 3 ns. The 16,128-channel digital resolution provides excellent peak definition when analyzing wide energy ranges with high-resolution germanium detectors. In four-fold coincidence experiments a dead time as low as 15% for each detector channel results in a coincidence dead-time loss of 48%. Consequently, the live-time clock included in each Model AD114 is vital for calculating the true coincidence rate. The flexibility of the computer-controlled functions also makes the Model AD114 useful for silicon charged-particle detectors, scintillation detectors, proportional counters, and ionization chambers.

The dc-coupled analog input employs a peak amplitude stretcher, and accepts pulses in the linear range from 0 to +10 V. A 14-bit, successive-approximation ADC with sliding scale linearization provides the conversion to a digital number in 5 µs. The analog input accepts unipolar and bipolar pulses from standard spectroscopy amplifiers with shaping times from 0.25 to 20 µs. A differential input is incorporated to suppress ground-loop noise when connected to systems with multiple power supplies and grounds. CAMAC control of the input dc-offset, the lower-level discriminator, and the upper-level discriminator facilitates computer adjustment of the analog operating parameters.

Several types of gating are provided. For coincidence experiments employing the FERAbus readout, the master GATE input is delivered to all ADCs through the ECL CONTROL bus. This gate synchronizes the ADCs on coincident events and forces all ADCs to wait for a common clear at the end of event readout. In the CAMAC readout mode, the master GATE can be delivered to all ADCs as a TTL input on the front-panel LEMO connector. Using only the master GATE to define coincident events can lead to the random analysis of unrelated events at individual ADC inputs. These unwanted events can be suppressed by providing a LOCAL GATE input to each ADC only when there is a valid, coincident event at the ADC INPUT. The rear-panel PUR input is an anticoincidence gate for use with the pile-up rejector logic pulse from a spectroscopy amplifier. It can also be used as a general-purpose veto input. CAMAC commands permit enabling and disabling the module's response to the master GATE or the LOCAL GATE inputs. This is useful when selecting the coincidence mode or the singles mode for the Model AD114 under CAMAC control.

Additional modes selectable by CAMAC command are: CAMAC or FERAbus readout, zero-suppression or no zero-suppression during readout, overflow suppression, and singles or coincidence analysis.

Each Model AD114 includes its own live-time clock for correction of dead-time losses. The Gedcke-Hale live-time clock¹ corrects for the pile-up losses occurring in the spectroscopy amplifier, and for the dead time of the ADC conversion and readout. It provides complete dead-time correction for amplifiers directly presenting their unipolar output pulse, and/or amplifiers providing the appropriated BUSY and PUR logic signals. Via CAMAC commands, the live-time clock can be reset, started, stopped, and read without stopping.

The Model AD114 is compatible with the standard LeCroy FERA control and data output busses. This system can provide very fast readout of the ADCs with non-zero events in a CAMAC crate full of ADCs. For both data acquisition and readout, the control bus synchronizes all ADCs with the experiment's master trigger. This permits identification of all the ADC outputs from the same event and their subsequent assimilation into a common block of data. To the standard FERAbus features, ORTEC has added the ability to select the singles or coincidence analysis mode for any Model AD114. This feature allows checking the functionality of a detector via the singles spectrum at any time during an experiment. The Model AD114 can be mixed with the ORTEC Model AD413A in the same FERAbus readout loop.

Normally, all the ADCs in the crate are connected to a LeCroy Model 4301 FERA Driver for control and readout (Fig. 1). The FERA Driver, in turn, delivers the data to either a LeCroy Model 4302 Dual Port Fast Memory in CAMAC, or a CES Model HSM8170 High Speed Memory in VMEbus. Both memories operate in the list mode to assemble the block of coincident events for further processing by an event builder. To facilitate making the interconnections between the FERAbus modules, the C-ECLBUS Cable Kit is recommended as a separately ordered accessory. This kit contains the cables and connectors needed for a crate full of FERAbus modules.

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